Project 1 - 40-V to 80-V adjustable output voltage boost reference design for LIDAR applications

Question:

Description: To design a non-synchronous boost controller to provide an adjustable output of between 40 V and 80 V capable of delivering a maximum of 100 mA of current to the load. This is an automotive design intended to power various applications such as LiDAR systems, which require an adjustable voltage supply.

Question:

1. How will you decide the layer stack up.
2. How do you calculate the trace width, via size and trace length.
3. What is the drawback of having 2 layers PCB?

Answers:

1)

- PCB layer stack-up, also called layer build-up, is the arrangement of insulating layers and conductive layers (copper layers) that make up the PCB before PCB layout design. Several insulating layers and copper layers are stacked together through the “prepreg” to generate a multiple-layered PCB.

- The Layer count is defined by Rounting constraint, Density, Package type, Power delivery etc

-How ever the stackup layer is more concerned with the electrical type of each layer in the PCB.

-For maximum efficiency and minimum losses and EMI, it is important to plan the right stack up of layers before starting the fabrication process. 4-layer PCB is the most common stack-up arrangement used in modern electronics.

- For such a simple circuit a 2 or 4 layer stackup could be choosen. For maximum efficiency and minimum losses and EMI, a 4 layer stackup will be chooseny, since a 2 and 4 layer stackup have little cost difference but 4 layer stackup offer more efficiency.

2)

- Trace width is an important design parameter in PCB design. Adequate trace width is necessary to ensure the desired amount of current can be transported without overheating and damaging your board. A higher current requires thicker traces while a thicker copper weight allows for thinner traces.

Trace widths are often measured in mils, or thousands of an inch. A standard trace width for an ordinary signal (no special requirements) may be in the 7-12 mil range and be as long as a few inches, but there are many things that should be considered when defining the width and length of a trace.

The Trace Width is calculated: Width[mils] = Area[mils²] / ( Thickness[oz] * 1.378[mils/oz] )

Using online calculator for Trace width, the following results was obtained for our trace width

- When it comes to the Via size, we have to take into concidaration the via diameter and the via drill diameter. The Via drill is the finished size of the actual hole. diameter is the outer diameter of the copper surrounding the hole. The annular ring of the via will be the (diameter-drill)/2.

Absolute via sizes are not really specified according to industry standards. Instead, only the minimum sizes are specified based on the size of the component that will be mounted on the via. These standards must be followed if your PCB is to be compliant. The IPC-2222 standard specifies minimum hole diameters for plated through-hole vias for different classes of vias as follows:

• Minimum hole size = Maximum lead diameter + 0.25 mm (Level)
• Minimum hole size = Maximum lead diameter + 0.20 mm (Level B)
• Minimum hole size = Maximum lead diameter + 0.15 mm (Level C)

The lead diameter refers to the size of pin on a component that will appear on a particular plated through-hole via. In addition to standard via sizes, there are also standardized pad sizes that should be used in compliant PCBs. The IPC-2221A standard defines minimum pad sizes for vias as a + 2b + c, where a is the maximum hole diameter, minimum annular ring size, and c is the fabrication tolerance. The fabrication tolerance depends on whether the vias are mechanically drilled or laser drilled, as well as individual process and machining parameters.

The maximum fabrication tolerances are defined as 0.6 mm for Level A, 0.5 mm for Level B, and 0.4 mm for Level C. If a manufacturer’s tolerance is less than 0.4 mm, then vias can meet the highest level of certification. Manufacturers usually have different processes that are designed to meet each level.

Each of the levels above refers to a particular “density level.” Level A is used for boards component with low density and components with a large footprint. Level B is a standard density level that is suitable for reflow, wave, drag, or dip soldering. Finally, Level C is used forHDI boards with very small, dense components.

*The goal is to create a via with at least as much conductive area within the hole as the trace connecting to it We could make a drill size diameter the same as the width of the trace, and the pad size roughly twice the diameter. This gives us a little bit of leeway in case our board is too dense to allow these sizes, and we need to adjust them.

- PCB trace length matching is exactly as its name suggests: you are matching the lengths of two or more PCB traces as they are routed across a board. These traces could be one of the following: Multiple single-ended traces routed in parallel. Each end of a differential pair.

In this example, we will asumme the normal FR4 material with a dielectric constant of 4 is used on the PCB with a differential clock rate of 1.2GHz (i.e., 833ps clock period):

Max skew in time delay = +/-2.5% of the 833ps clock period = 20.825ps FR4 Er = 4, Er_{eff =} 2.92

So, for strip lines, the maximum skew should be less than +/- (20.825/(85*SQT(4))=+/-0.1225 in = +/- 122.5 mil.

For microstrips, the maximum skew should be less than +/- (20.825/(85*SQT(2.92)) = +/-0.1433 in = +/- 143.3 mil.

- The main drawback of 2 Layer PCBs is that they are not as durable as other types of PCBs. In other words, 2 Layer PCBs are also more susceptible to crosstalk and noise than other types of PCBs.