Project 2 - SiC/IGBT isolated gate driver reference design with thermal diode and sensing FET

Designing an IGBT or SiC isolated gate driver power stage with advanced protection features requires a thorough understanding of the system requirements, as well as the properties and limitations of the components being used.The power stage should support a single phase from a traction inverter and provide a high level of safety features. The integrated thermal diode and sensing FET of the IGBT module should be utilized to provide fast and accurate protection. The design should also include bias supplies with output voltage monitoring, isolated DC bus sensing in redundant circuits, temp sensing for high side and low side drivers, PWM gate signal monitoring, and fault signal injection diagnostics.The supply should be designed to accept a wide input range of 4.5V to 65V DC and deliver up to 180mA output current. The isolated gate driver should have up to ±10A drive strength and include an analog to PWM converter, which can be utilized for temperature and voltage sensing.Some additional considerations for designing an IGBT or SiC isolated gate driver power stage with advanced protection features include:

Circuit topology: The circuit topology should be carefully chosen to ensure that the gate driver can provide the necessary voltage and current to drive the IGBT or SiC module. The topology should also be designed to minimize switching losses and improve efficiency.
Isolation: The gate driver should provide high levels of isolation to ensure safety and reliability. The isolation can be achieved through the use of transformers, optocouplers, or other isolation techniques.
Thermal management: The gate driver and power stage should be designed with effective thermal management in mind to prevent overheating and ensure long-term reliability. Thermal simulations should be conducted to ensure that the system can operate within safe temperature limits.
PCB layout: The PCB layout should be carefully designed to minimize noise and interference and ensure that the system operates correctly. High-speed signals, such as PWM gate signals, should be routed carefully to prevent ringing and other signal integrity issues.
Testing and validation: The gate driver and power stage should be thoroughly tested and validated to ensure that they meet the desired performance and safety specifications. Testing should include both functional testing and stress testing to ensure that the system can operate under a variety of conditions.

The layer stack-up for the PCB design of the IGBT or SiC isolated gate driver power stage with advanced protection features will depend on a number of factors, such as the number of layers required to accommodate the circuit topology and the need for noise and interference reduction. Here are some steps to decide the layer stack-up:

Determine the number of layers required: The number of layers required for the PCB design will depend on the complexity of the circuit and the number of components that need to be accommodated. Typically, a minimum of four layers is required for a power stage design, but the number can vary depending on the specific requirements of the design.
Identify high-speed signals: High-speed signals, such as PWM gate signals, should be routed on separate signal layers to reduce noise and interference. For example, a two-layer stack-up with a ground plane and a signal layer can be used to route high-speed signals.
Plan for power and ground planes: A power and ground plane should be included in the PCB design to provide a low impedance path for current flow and reduce noise. A four-layer stack-up with power and ground planes on the inner layers can be used to provide sufficient power distribution and reduce noise.
Consider signal integrity and noise reduction: To ensure signal integrity and reduce noise, a dedicated layer can be included for signal return paths. This can be achieved by adding a signal reference layer, which is connected to the ground plane and used to provide a low impedance return path for signals.
Plan for component placement: The component placement can have an impact on the layer stack-up. The placement of high-power components, such as the IGBT or SiC module, can influence the location of power and ground planes, while the placement of high-speed components, such as the gate driver and PWM signals, can influence the location of signal layers.
Conduct simulations: Before finalizing the layer stack-up, simulations should be conducted to ensure that the design meets the desired performance specifications. Signal integrity simulations can be used to validate the stack-up and identify any issues with noise or interference.

Overall, the layer stack-up for the PCB design of the IGBT or SiC isolated gate driver power stage should be carefully planned and optimized to meet the specific requirements of the design, including power distribution, signal integrity, and noise reduction.