Project 2 - SiC/IGBT isolated gate driver reference design with thermal diode and sensing FET
- How will you decide the layer stack up.
Answer:
A stackup is the arrangement of layers of copper and insulators that make up a PCB before designing the final layout of the board. Stack-up refers to the arrangement of copper layers and insulating layers that make up a PCB prior to board layout design. While a layer stack-up allows you to get more circuitry on a single board through the various PCB board layers, the structure of PCB stack-up design confers many other advantages. For such a designe a 4 or 6 stack layer will be chosen for the simplicity of the circuit and because the output delivered current is not of hight but ±10A drive strength for the gates of the IGBT .
2) How do you calculate the trace width, via size and trace length?
Ans:-
The important factors to consider when selecting a trace width include:
- The current capacity of the trace
- Space availability and manufacturing limitations
- Trace termination
- Impedance
Then, the Width is calculated: Width[mils] = Area[mils⊃2;] / ( Thickness[oz] * 1.378[mils/oz] ). how ever there are the Trance width could be calculated automaticaliy online after giving important parameters such as current, temperature, trace length. For this example we will assume the 6 layer stackup PCB with a thicknes of 1.6mm.
Absolute via sizes are not really specified according to industry standards. Instead, only the minimum sizes are specified based on the size of the component that will be mounted on the via. These standards must be followed if your PCB is to be compliant. The IPC-2222 standard specifies minimum hole diameters for plated through-hole vias for different classes of vias as follows:
- Minimum hole size = Maximum lead diameter + 0.25 mm (Level)
- Minimum hole size = Maximum lead diameter + 0.20 mm (Level B)
- Minimum hole size = Maximum lead diameter + 0.15 mm (Level C)
In addition to standard via sizes, there are also standardized pad sizes that should be used in compliant PCBs. The IPC-2221A standard defines minimum pad sizes for vias as a + 2b + c, where a is the maximum hole diameter, minimum annular ring size, and c is the fabrication tolerance. The fabrication tolerance depends on whether the vias are mechanically drilled or laser drilled, as well as individual process and machining parameters.The maximum fabrication tolerances are defined as 0.6 mm for Level A, 0.5 mm for Level B, and 0.4 mm for Level C. If the manufacturer’s tolerance is less than 0.4 mm, then the vias can meet the highest level of certification. Manufacturers usually have different processes that are designed to meet each level.Each of the levels above refers to a particular “density level.” Level A is used for boards component with low density and components with a large footprint. Level B is a standard density level that is suitable for reflow, wave, drag, or dip soldering. Finally, Level C is used for HDI board with very small, dense components.
3) What all you do to avoid heating of component in a 4 layer PCB?
Ans:-
4) Advantage of multilayer PCB?
Ans:-
These types of printed circuit boards allow for unprecedented miniaturization, with a very high component density rate. Multilayer PCBs are printed circuits made up of more than two layers. They must therefore have at least three layers of conductive material within the insulating material. One of the major reasons for multiple layer is Increased Durability: Having more layers means the board is thicker and, therefore, more durable than single-sided PCBs. This is another reason adding functionality through additional layers is preferable to increase the dimensions of a single layer.but how ever Multilayer PCB boards manufacturing is more expensive as compared to double layer and single layer PCBs. Multilayer PCB board design is difficult so we need more time to work out any possible problems. They have a complex manufacturing process so there are high labor costs.