Challenge

Project 1 - Wiper control system and Vehicle speed calculation for ABS using Wheel Speed sensor

About V & V model

V model known as verification & validation model

it is derived from waterfall model

it carry iterative testing for which each stage is test & check & wethere it meets customer requirement

A. Vehicle speed calculation for ABS using Wheel Speed sensor

1.Simulink model

2. SLDD

3.Requirement tagging

4.fixed point tollbox

5.Model advisor - JMAAB compliance

6.SLDV error detection

7 Functional test case, MIL, SIL harness, coverage Reports

8 Run the analyzer test > confirm the test generation setting > test gen. report > run the harness > Analyze the coverage test result

9.Auto-code generation report, .c & .h codes

apps > build code

/*
 * File: module_three_project_one_question_one.c
 *
 * Code generated for Simulink model 'module_three_project_one_question_one'.
 *
 * Model version                  : 1.23
 * Simulink Coder version         : 9.5 (R2021a) 14-Nov-2020
 * C/C++ source code generated on : Wed Sep 28 16:27:36 2022
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Intel->x86-64 (Windows64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#include "module_three_project_one_question_one.h"
#include "module_three_project_one_question_one_private.h"

/* Named constants for Chart: '/Chart' */
#define module_three_project__IN_Mode10 ((uint8_T)2U)
#define module_three_project__IN_Mode11 ((uint8_T)3U)
#define module_three_project__IN_Mode12 ((uint8_T)4U)
#define module_three_project__IN_Mode13 ((uint8_T)5U)
#define module_three_project_o_IN_Mode1 ((uint8_T)1U)
#define module_three_project_o_IN_Mode2 ((uint8_T)6U)
#define module_three_project_o_IN_Mode3 ((uint8_T)7U)
#define module_three_project_o_IN_Mode4 ((uint8_T)8U)
#define module_three_project_o_IN_Mode5 ((uint8_T)9U)
#define module_three_project_o_IN_Mode6 ((uint8_T)10U)
#define module_three_project_o_IN_Mode7 ((uint8_T)11U)
#define module_three_project_o_IN_Mode8 ((uint8_T)12U)
#define module_three_project_o_IN_Mode9 ((uint8_T)13U)
#define module_three_project_o_IN_START ((uint8_T)14U)

/* Block states (default storage) */
DW_module_three_project_one_q_T module_three_project_one_que_DW;

/* External inputs (root inport signals with default storage) */
ExtU_module_three_project_one_T module_three_project_one_ques_U;

/* External outputs (root outports fed by signals with default storage) */
ExtY_module_three_project_one_T module_three_project_one_ques_Y;

/* Real-time model */
static RT_MODEL_module_three_project_T module_three_project_one_que_M_;
RT_MODEL_module_three_project_T *const module_three_project_one_que_M =
  &module_three_project_one_que_M_;

/* Model step function */
void module_three_project_one_question_one_step(void)
{
  /* Chart: '/Chart' incorporates:
   *  Inport: '/FR'
   *  Inport: '/Fl'
   *  Inport: '/RL'
   *  Inport: '/RR'
   */
  if (module_three_project_one_que_DW.is_active_c1_module_three_proje == 0U) {
    module_three_project_one_que_DW.is_active_c1_module_three_proje = 1U;
    module_three_project_one_que_DW.is_c1_module_three_project_one_ =
      module_three_project_o_IN_START;
  } else {
    switch (module_three_project_one_que_DW.is_c1_module_three_project_one_) {
     case module_three_project_o_IN_Mode1:
     case module_three_project__IN_Mode10:
     case module_three_project__IN_Mode11:
     case module_three_project__IN_Mode12:
     case module_three_project__IN_Mode13:
     case module_three_project_o_IN_Mode2:
     case module_three_project_o_IN_Mode3:
     case module_three_project_o_IN_Mode4:
     case module_three_project_o_IN_Mode5:
     case module_three_project_o_IN_Mode6:
     case module_three_project_o_IN_Mode7:
     case module_three_project_o_IN_Mode8:
     case module_three_project_o_IN_Mode9:
      break;

     default:
      /* case IN_START: */
      if ((module_three_project_one_ques_U.Fl > 0.0) &&
          (module_three_project_one_ques_U.FR > 0.0) &&
          (module_three_project_one_ques_U.RL > 0.0) &&
          (module_three_project_one_ques_U.RR > 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project_o_IN_Mode1;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          (((module_three_project_one_ques_U.Fl +
             module_three_project_one_ques_U.FR) +
            module_three_project_one_ques_U.RL) +
           module_three_project_one_ques_U.RR) / 4.0;
      } else if (((module_three_project_one_ques_U.Fl == 0.0) &&
                  (module_three_project_one_ques_U.FR == 0.0) &&
                  (module_three_project_one_ques_U.RL == 0.0)) ||
                 ((module_three_project_one_ques_U.RR == 0.0) &&
                  (module_three_project_one_ques_U.RL == 0.0) &&
                  (module_three_project_one_ques_U.RR == 0.0)) ||
                 ((module_three_project_one_ques_U.Fl == 0.0) &&
                  (module_three_project_one_ques_U.FR == 0.0) &&
                  (module_three_project_one_ques_U.RR == 0.0)) ||
                 ((module_three_project_one_ques_U.RL == 0.0) &&
                  (module_three_project_one_ques_U.RR == 0.0) &&
                  (module_three_project_one_ques_U.Fl == 0.0))) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project_o_IN_Mode2;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed = 0.0;
      } else if ((module_three_project_one_ques_U.Fl == 0.0) &&
                 (module_three_project_one_ques_U.FR == 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project_o_IN_Mode3;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          (module_three_project_one_ques_U.RL +
           module_three_project_one_ques_U.RR) / 2.0;
      } else if ((module_three_project_one_ques_U.Fl == 0.0) &&
                 (module_three_project_one_ques_U.RL == 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project_o_IN_Mode4;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          (module_three_project_one_ques_U.RR +
           module_three_project_one_ques_U.FR) / 2.0;
      } else if ((module_three_project_one_ques_U.Fl == 0.0) &&
                 (module_three_project_one_ques_U.RR == 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project_o_IN_Mode5;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          (module_three_project_one_ques_U.FR +
           module_three_project_one_ques_U.RL) / 2.0;
      } else if ((module_three_project_one_ques_U.FR == 0.0) &&
                 (module_three_project_one_ques_U.RR == 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project_o_IN_Mode6;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          (module_three_project_one_ques_U.RL +
           module_three_project_one_ques_U.Fl) / 2.0;
      } else if ((module_three_project_one_ques_U.FR == 0.0) &&
                 (module_three_project_one_ques_U.Fl == 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project_o_IN_Mode7;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          (module_three_project_one_ques_U.RL +
           module_three_project_one_ques_U.RR) / 2.0;
      } else if ((module_three_project_one_ques_U.RL == 0.0) &&
                 (module_three_project_one_ques_U.RR == 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project_o_IN_Mode8;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          (module_three_project_one_ques_U.Fl +
           module_three_project_one_ques_U.FR) / 2.0;
      } else if ((module_three_project_one_ques_U.Fl == 0.0) &&
                 (module_three_project_one_ques_U.FR == 0.0) &&
                 (module_three_project_one_ques_U.RL == 0.0) &&
                 (module_three_project_one_ques_U.RR == 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project_o_IN_Mode9;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed = 0.0;
      } else if ((module_three_project_one_ques_U.FR == 0.0) &&
                 (module_three_project_one_ques_U.Fl > 0.0) &&
                 (module_three_project_one_ques_U.RR > 0.0) &&
                 (module_three_project_one_ques_U.RL > 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project__IN_Mode10;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          ((module_three_project_one_ques_U.RL +
            module_three_project_one_ques_U.Fl) +
           module_three_project_one_ques_U.RR) / 3.0;
      } else if ((module_three_project_one_ques_U.RR == 0.0) &&
                 (module_three_project_one_ques_U.FR > 0.0) &&
                 (module_three_project_one_ques_U.Fl > 0.0) &&
                 (module_three_project_one_ques_U.RL > 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project__IN_Mode11;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          ((module_three_project_one_ques_U.RL +
            module_three_project_one_ques_U.FR) +
           module_three_project_one_ques_U.RR) / 3.0;
      } else if ((module_three_project_one_ques_U.RR == 0.0) &&
                 (module_three_project_one_ques_U.FR > 0.0) &&
                 (module_three_project_one_ques_U.Fl > 0.0) &&
                 (module_three_project_one_ques_U.RL > 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project__IN_Mode12;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          ((module_three_project_one_ques_U.Fl +
            module_three_project_one_ques_U.FR) +
           module_three_project_one_ques_U.RL) / 3.0;
      } else if ((module_three_project_one_ques_U.RL == 0.0) &&
                 (module_three_project_one_ques_U.RR > 0.0) &&
                 (module_three_project_one_ques_U.FR > 0.0) &&
                 (module_three_project_one_ques_U.Fl > 0.0)) {
        module_three_project_one_que_DW.is_c1_module_three_project_one_ =
          module_three_project__IN_Mode13;

        /* Outport: '/speed' */
        module_three_project_one_ques_Y.speed =
          ((module_three_project_one_ques_U.Fl +
            module_three_project_one_ques_U.FR) +
           module_three_project_one_ques_U.RR) / 3.0;
      }
      break;
    }
  }

  /* End of Chart: '/Chart' */
}

/* Model initialize function */
void module_three_project_one_question_one_initialize(void)
{
  /* (no initialization code required) */
}

/* Model terminate function */
void module_three_project_one_question_one_terminate(void)
{
  /* (no terminate code required) */
}

/*
 * File trailer for generated code.
 *
 * [EOF]
 */

10. Polyspace analysis report / outputs

11. Test manager reports – baseline & back-to-back testing

A. Base-line testing

step1: creating a baseline test suite name

adding (Reuirement + .slx file )

step2: creating input data

step3: copping the data from calculated sheet

step4: now mapped data

step5: now baseline file name cration

and one more extra option is available (sheet) , if we have some spesific test data then we add here

step6: by right click on test file we save it, then run

step7: by right click on test file we create report of our baseline-test

B. BACK-2-BACK TESTING

step1: create test file then delete case , save it ,right click on new select TEST FOR MODEL COMPONENT

step2: select your top level of your model ,then add it in SYSTEM , in COMPONENT it automatically take 1st subsysytem,then click NEXT

step3: since here we have multiple option for input for test input but we choose "Use Design Verifier to generate test input scenarios .Create inputs using Simulink Design Verifier" because the test here is totally autonnomus , click NEXT

step4: choose B2B testing , in this choose NORMAL>SIL>MCDC enable it ,click NEXT

step5: choose INPORTS for test harness and file format is EXCEL , click DONE

step6: automatically Harness is created and embedded in parent model

step7: in test manager add requuirement , enable record coverage ,rest every thing default

( we have give MCDC but when run sldv toolbox it choosen what kind of block is define for what objective, so what kind of mode is best suitable either it is MCDC/DECSION ,based on that it choose default DECSION block for particular algoritham )

step8: run the test , then right click on respected file to generate report

B. Wiper control system

1.Simulink model

2. SLDD

3.Requirement tagging

4.fixed point tollbox

5.Model advisor - JMAAB compliance

6.SLDV error detection

7 Functional test case, MIL, SIL harness, coverage Reports

8 Run the analyzer test > confirm the test generation setting > test gen. report > run the harness > Analyze the coverage test result

1	/*
2	 * File: ert_main.c
3	 *
4	 * Code generated for Simulink model 'module_three_project_wiper_control'.
5	 *
6	 * Model version                  : 1.21
7	 * Simulink Coder version         : 9.5 (R2021a) 14-Nov-2020
8	 * C/C++ source code generated on : Wed Sep 28 20:37:57 2022
9	 *
10	 * Target selection: ert.tlc
11	 * Embedded hardware selection: Intel->x86-64 (Windows64)
12	 * Code generation objectives: Unspecified
13	 * Validation result: Not run
14	 */
15	
16	#include 
17	#include               /* This ert_main.c example uses printf/fflush */
18	#include "module_three_project_wiper_control.h" /* Model's header file */
19	#include "rtwtypes.h"
20	
21	/*
22	 * Associating rt_OneStep with a real-time clock or interrupt service routine
23	 * is what makes the generated code "real-time".  The function rt_OneStep is
24	 * always associated with the base rate of the model.  Subrates are managed
25	 * by the base rate from inside the generated code.  Enabling/disabling
26	 * interrupts and floating point context switches are target specific.  This
27	 * example code indicates where these should take place relative to executing
28	 * the generated code step function.  Overrun behavior should be tailored to
29	 * your application needs.  This example simply sets an error status in the
30	 * real-time model and returns from rt_OneStep.
31	 */
32	void rt_OneStep(void);
33	void rt_OneStep(void)
34	{
35	  static boolean_T OverrunFlag = false;
36	
37	  /* Disable interrupts here */
38	
39	  /* Check for overrun */
40	  if (OverrunFlag) {
41	    rtmSetErrorStatus(module_three_project_wiper_c_M, "Overrun");
42	    return;
43	  }
44	
45	  OverrunFlag = true;
46	
47	  /* Save FPU context here (if necessary) */
48	  /* Re-enable timer or interrupt here */
49	  /* Set model inputs here */
50	
51	  /* Step the model */
52	  module_three_project_wiper_control_step();
53	
54	  /* Get model outputs here */
55	
56	  /* Indicate task complete */
57	  OverrunFlag = false;
58	
59	  /* Disable interrupts here */
60	  /* Restore FPU context here (if necessary) */
61	  /* Enable interrupts here */
62	}
63	
64	/*
65	 * The example "main" function illustrates what is required by your
66	 * application code to initialize, execute, and terminate the generated code.
67	 * Attaching rt_OneStep to a real-time clock is target specific.  This example
68	 * illustrates how you do this relative to initializing the model.
69	 */
70	int_T main(int_T argc, const char *argv[])
71	{
72	  /* Unused arguments */
73	  (void)(argc);
74	  (void)(argv);
75	
76	  /* Initialize model */
77	  module_three_project_wiper_control_initialize();
78	
79	  /* Attach rt_OneStep to a timer or interrupt service routine with
80	   * period 0.01 seconds (the model's base sample time) here.  The
81	   * call syntax for rt_OneStep is
82	   *
83	   *  rt_OneStep();
84	   */
85	  printf("Warning: The simulation will run forever. "
86	         "Generated ERT main won't simulate model step behavior. "
87	         "To change this behavior select the 'MAT-file logging' option.\n");
88	  fflush((NULL));
89	  while (rtmGetErrorStatus(module_three_project_wiper_c_M) == (NULL)) {
90	    /*  Perform other application tasks here */
91	  }
92	
93	  /* Disable rt_OneStep() here */
94	
95	  /* Terminate model */
96	  module_three_project_wiper_control_terminate();
97	  return 0;
98	}
99	
100	/*
101	 * File trailer for generated code.
102	 *
103	 * [EOF]
104	 */
105	

10. Polyspace analysis report / outputs

11. Test manager reports – baseline & back-to-back testing

A. Base-line testing

step1: creating a baseline test suite name

adding (Reuirement + .slx file )

step2: creating input data

step3: copping the data from calculated sheet

step4: now mapped data

step5: now baseline file name cration

and one more extra option is available (sheet) , if we have some spesific test data then we add here

step6: by right click on test file we save it, then run

step7: by right click on test file we create report of our baseline-test

B. BACK-2-BACK TESTING

step1: create test file then delete case , save it ,right click on new select TEST FOR MODEL COMPONENT

step2: select your top level of your model ,then add it in SYSTEM , in COMPONENT it automatically take 1st subsysytem,then click NEXT

step3: since here we have multiple option for input for test input but we choose "Use Design Verifier to generate test input scenarios .Create inputs using Simulink Design Verifier" because the test here is totally autonnomus , click NEXT

step4: choose B2B testing , in this choose NORMAL>SIL>MCDC enable it ,click NEXT

step5: choose INPORTS for test harness and file format is EXCEL , click DONE

step6: automatically Harness is created and embedded in parent model

step7: in test manager add requuirement , enable record coverage ,rest every thing default

( we have give MCDC but when run sldv toolbox it choosen what kind of block is define for what objective, so what kind of mode is best suitable either it is MCDC/DECSION ,based on that it choose default DECSION block for particular algoritham )

step8: run the test , then right click on respected file to generate report

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