The webinar will cover the following:

• VLSI Industry
• Typical SOC Design
• SOC Technology - Silicon Wafer
• SOC Testing - Automatic Test Equipments
• Manufacturing Defects
• What is DFT? Why do we need DFT?
• SOC Design Flow
• DFT Flow
• Faults in a Circuit
• Table of Contents
• Transition Delay Testing
• DFT Flow
• Insertion (Scan)
• Generation (ATPG)
• Validation (Post-Silicon)
• Scan Issue
• Scan Live Issue
• Case Study
• Fix
• Table of Contents
• DFT Goals
• Role of a DFT Engineer
• DFT Tools Used
• Session’s Overall Structure
• Opportunities for DFT Engineers

Learning Outcomes:

• Minimal/resolve DRC errors and warnings
• Minimize test generation efforts
• Minimize hardware or software needed for test
• Make the device self-testing as much as possible

About : A DFT Research Engineer and another 4+ years as an Embedded System Design Engineer.

• Experience in DFT Insertion and Validation - Scan, Compression, ATPG, Simulation and Pattern Retargeting.
• Hands-on experience in Scan/EDT/ATPG DRC analysis. Also, in analyzing and improving fault/test coverage.
• Proficiency in devising novel path delay fault model and implementing them on a customized signal integrity-aware ATPG flow.
• Strong scripting (TCL/PERL) and automation skills for efficient handling of ATE data.
• Experience in designing and developing analog and digital circuit products, programming microcontrollers, prototype board bring-up, product testing and resolving field failures.